Processes for fabricating a combination of bipolar and field effect transistors (FET) on the same semiconductor chip are disclosed in U.S. Pat. No. 4,824,796 to Chiu et al. and U.S. Pat. No. 4,784,971 to Chiu et al. In processes, stacks of appropriate material formed on a semiconductor substrate, e.g., a silicon wafer, over those areas of the substrate which will eventually correspond to the gate electrodes of the MOS devices and the emitter electrode of the bipolar devices. These stacks (such as 51, 52, and 53 in FIG. 1) include a layer of doped polycrystalline material 41, and an etch stop layer 42 such as silicon dioxide or silicon nitride. These stacks also include a second layer of polysilicon material 43. Stacks 51, 52, and 53 are formed by depositing layers of material 41, 42, and 43 and then selectively removing portions of those layers to form the stacks.
A conformal oxide 61 is then formed over the entire wafer to a thickness of about 200 nm as indicated in FIG. 2. An anisotropic reactive ion etching process is then used to remove potions of the oxide. This reactive ion etching removes the oxide that was deposited over the tops of the stocks 51, 52, and 53 and the oxide on the substrate surface between the walls 71 of oxide adjacent to the stacks, which result in silicon dioxide walls 71 surrounding the stacks 51, 52, and 53 as depicted in FIG. 3.
The substrate is then cleaned and a polycrystalline silicon (polysilicon) layer 81 having a thickness of about 200 nm is deposited over the entire wafer as shown in FIG. 4. A photolithography process is used to remove the portions of the polycrystalline layer 81 that is deposited between stacks 51, 52, and 53. The portions of the polysilicon material 81 that are removed by this step 82 are set off by dashes in FIG. 4. The polysilicon material is etched isotropically so that the individual devices formed from stacks 51, 52, and 53 are electrically isolated.
Dopant is introduced into the polysilicon layer by first masking those areas of the device that are not desired to be doped with a photoresist (not shown) and then introducing dopant into the unmasked regions (not shown). The photoresist is then stripped from the device. This procedure is performed once to introduce p-type dopant into certain portions of the polysilicon martial 81 and once to introduce n-type dopant into certain other portions of the polysilicon material.
The entire substrate is then covered with a silicon nitride deposition layer 102 having a thickness of about 80 nm. This layer of silicon nitride is designated as 102 in FIG. 5A. The silicon nitride layer 102 conforms to the polysilicon layer 81, and protects the polysilicon 81 in a subsequent step during which a photoresist layer is selectively etched back.
A planar photoresist layer 101, as depicted in FIG. 5A, with a uniform thickness of 3 to 5 microns is formed over the entire substrate 10. This photoresist layer 101 is then etched back to a point where the portion of the silicon nitride layer 102 on the top of the stacks 51, 52 and 53 is clearly exposed. The exposed portion of the nitride layer 102 is then removed. After the exposed nitride layer 102 is removed, the remaining photoresist layer 101 is hardened and the polysilicon 81 above the stacks is selectively removed. The remaining photoresist material 101 is then removed. The resulting structure is depicted in FIG. 5B.
In the above process, it is important that only those portions of the nitride layer 102 and the polysilicon layer 81 directly above the stacks be removed. Therefore, it is important that the photoresist be of uniform thickness over the stacks. Also, it is advantageous if the resist material is much thicker over the areas of the substrate between the stacks, so that the surface of the substrate in these areas is not etched when the silicon nitride and polysilicon material from the tops of the stacks is being removed. As illustrated in FIG. 6, it is difficult to form a layer of uniform thickness over a surface on which the stacks are not spaced evenly. As illustrated in FIG. 6, the resist is one thickness 107 over the tops of the group of stacks 51, 52, and 53. However, the resist is another thickness, 108, over remote stack 54. Thickness 108 is therefore much less than thickness 107. This thickness differential leads to nonuniform processing as between the clustered stacks, 51, 52, and 53 and the remote stack 54. Furthermore, the thickness of the resist 101 between remote stack 54 and clustered stack 51 is much less than the thickness of the resist 101 between clustered stacks 51 and 52. Such nonuniformity is not desirable because it leads to overetch of some material stacks, the oxide and polysilicon materials surrounding these stacks, or the materials between the stacks. As a result, the performance of the discrete devices formed from these stacks may be degraded. Under these conditions, some improvement in the planarization process is desired.